Recently, a semiconductor memory device, particularly a dynamic random access memory (referred to as "a DRAM") device tends to be high integrated more rapidly than other memory devices. Many makers have made every endeavor to implement an ultra high integration density DRAM (for example, having the capacity of 1-giga bits). One of such tries lays out within a given area a sense amplifier block (14, refer to FIG. 1) consisting of bit line precharge and isolation sections, P- and N-latch sense amplifier sections, an input/output gating section, etc.
It is needless to say that plural bit lines provided in the DRAM may be positioned by a type of an open bit line structure, a folded bit line structure, or the other. Typically, in such a DRAM that the bit lines are arranged in accordance with the folded bit line structure, there is disposed the sense amplifier block associated with a pair of bit lines within a width (or pitch) in which four bit lines are positioned. As well known, a memory cell array of the DRAM consists of a plurality of memory cell blocks, and sense amplifier blocks are laid out between two adjacent memory cell blocks so as to share each pair of bit lines provided respectively in the two adjacent memory cell blocks.
The higher the integration density of the DRAM, the shorter the distance (or space) between any two adjacent bit lines through which the data stored in the memory cell block is read to be amplified by a sense amplifier block. In case that the distance between two adjacent bit lines becomes shorter according to tendency of high integration density, an area in which one sense amplifier block is laid out (hereinafter, referred to as an unit area) also has to be reduced. However, it is impossible that the sense amplifier block for us in the DRAM of an ultra high integration density is arranged within the unit area thus reduced by use of present process and design techniques. Therefore, it is required a new sense amplifier block layout capable of being positioned within the unit area thus reduced.